Lift-off processes are well known in semiconductor device manufacturing. They were used early in silicon LSI processing until etch processes became the techniques of choice for VLSI technology. Etch processes can provide high definition patterns if the etch selectivity between the material being etched and other exposed materials is high. Etch techniques have been developed in silicon technology that provide good etch selectivity for the material systems of interest, but acceptable etch selectivity in III-V processing has been difficult to obtain. Accordingly, lift-off patterning techniques are used in critical patterning steps in the manufacture of many Ill-V devices.
In III-V device technology, the surface topography is typically severe. Vertical steps may be comparable in dimension to the spacing between features being defined. This is partly attributable to the fact that bipolar transistors are prominently used in III-V integrated circuits, and bipolar devices typically have mesa structures. Due to this factor multi-level resists, with at least one planarizing level, are typically used for lift-off in III-V IC processing.
Because surface topography in III-V device technology is so severe, edge definition becomes a critical issue. If the aspect ratio (height to width) of features being defined is large, variations in edge definition, which can be comparable in size to the feature thickness, may span the spacing between features. If that occurs, shorts result.
Much effort has gone into development of bilayer and trilayer resist schemes to overcome these problems. Bilayer processes involve a dual resist scheme, with a thick underlying resist for planarizing the structure, followed by another type of resist or contrast enhancement layer. The upper resist layer typically forms an overhang on top which is a common feature of multilayer resist processes. The overhang creates a positive discontinuity between regions of the deposited metallization layer as it steps from one level to another. The discontinuity insures lift-off of the metal deposited on the upper level of the multilevel resist.
Two layer resist schemes have drawbacks, often caused by mixing of the resist materials, thereby impairing edge definition and making it difficult to obtain a uniform overhang over large areas. See S. Zhang, et al, 4.sup.th International Conference on Solid-state and Integrated Circuit Technology, Proceedings (Cat. No. 95TH8143), G L Baldwin, Z Li, C C Tsai, and J. Zhang, ed. New York, N.Y. IEEE p. 41-43 (1995). In addition, some two layer processes use chlorobenzene, a hazardous and environmentally undesirable material. See R. Williams, Gallium Arsenide Processing Techniques (Artech House, Dedham, Mass., 1984), and P Kalee Prasad and J Narain, "Improved Lift-off Techniques for Thick Aluminum Metallization", Semiconductor Devices (Proc. SPIE Vol. 2733), K Lai, ed (Narosa Publishing House, New Delhi, India) 499 (1995).
Three layer resist processes avoid the resist mixing problem by using an intermediate transfer layer to segregate the resist layers. See for example, "Lift-Off Process for Achieving Fine-Line Mettalization", A A Milgram, J. Vac. Sci. Technol. B1 (2), 490 (1983); "Trilayer Lift-Off Metallization Process Using Low Temperature Deposited SiN.sub.x ", J R Lothian, F Ren, S J Pearton, U K Chakrabarti, C R Abernathy and A Katz, J. Vac. Sci. Technol. B10 (6), 2361 (1992); S P Lyman, J L Jackel and P L Liu, "Lift-off of Thick Metal Layers Using Multilayer Resist", J. Vac. Sci. Technol. 19 (4), 1325 (1981). But trilayer resist processes also have drawbacks. Some of the techniques described in the references cited above use a Ge transfer layer. Ge transfer layers obscure wafer alignment marks, thus limiting the use of stepper based technology. Ge is also difficult to see through when using contact lithography. Moreover, many trilayer techniques involve the use of thick planarizing layers as the first layer, which may not be compatible with the solvent systems used with resists such as polymethylglutarimide (PMGI).